In the year 2004 SETS has established Hardware Security Research Group (HSRG). Activities that are specifically focused in this lab are:
1. Hardware development environment facility is used to support the following activities:
  • Realization of secure communication system in FPGA based hardware platform like bulk encryption unit.
  • Realization of proof of concept lab prototype for network security appliances like Denial of Service (DoS) detection and mitigation techniques in FPGA based hardware platform.
  • Realization of cryptographic algorithms on FPGA for side channel analysis and optimization purpose.
2. Side Channel Analysis experiment set-up was established at SETS in 2007 in association      with TU Graz, Austria. The types of Side Channel analysis that are specifically focused are:
  • Simple Power Analysis (SPA), and
  • Differential Power analysis (DPA)

    There are three phases in performing SPA/DPA, such as data acquisition, key hypotheses, and key recovery. SETS has the evaluation platform and analysis set-up for performing all three phases.

      Currently, HSRG focuses on secure implementation of cryptographic algorithms against SPA and DPA attacks. This expertise shall be used to implement indigenous algorithm in a secured manner for any communication systems. HSRG is also exploring the possibilities of extending its research in hardware Trojan.


For further details please contact: asuganya[at]setsindia[dot]net

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